Search - FPGA DDS

[Other] fpga

Description: 大唐公司的内部学习教程，很好的介绍了可编程器件的学习经验-Datang company s internal learning curricula, introduced a very good learning experience programmable devices
Platform: | Size: 966656 | Author: 张宁 | Hits:

[Other] DDS

Description: 基于DDS技术的函数波形发生器设计，适合用fpga设计波形发生器用-Based on DDS technology function waveform generator design, suitable for FPGA design with Waveform Generator
Platform: | Size: 1682432 | Author: | Hits:

Description: FPGA内AM调制工程。内带调制波、载波生成。关键词：FPGA verilog AM DDS-AM modulation works within the FPGA. Within the band modulation wave generated carrier. Key words: FPGA verilog AM DDS
Platform: | Size: 1687552 | Author: baixiangzhou | Hits:

[VHDL-FPGA-Verilog] FPGA_signal_general

Description: 摘要：介绍了直接数字频率合成 (DDS) 技术的基本原理，给出了基于Altera公司FPGA器件的一个三相正弦信号发生器的设计方案，同时给出了其软件程序和仿真结果。仿真结果表明：该方法生成的三相正弦信号具有对称性好、波形失真小、频率精度高等优点，且输出频率可调。关键词：直接数字频率合成；现场可编程门阵列；FPGA；三相正弦信号-Abstract: Direct Digital Synthesis (DDS) technology, the basic principles are given Altera-based FPGA devices the company a three-phase sinusoidal signal generator design program, at the same time give its software programs and simulation results. The simulation results show that: the method to generate three-phase sinusoidal signal with good symmetry, waveform distortion small, the frequency of high precision, and adjustable output frequency. Key words: direct digital synthesizer field programmable gate array FPGA three-phase sinusoidal signal
Platform: | Size: 101376 | Author: 赵文 | Hits:

[VHDL-FPGA-Verilog] key_matrix44

Description: FPGA EP1C6Q240C8 4*4键盘模块 4*4矩阵键盘，采用扫描方式检测按键-FPGA EP1C6Q240C8 4* 4 keyboard module 4* 4 matrix keyboard, using scanning detection button
Platform: | Size: 278528 | Author: lan | Hits:

[VHDL-FPGA-Verilog] ddszh

Description: 基于FPGA的DDS正弦信号发生器,信号失真小，频率稳定，可调-FPGA DDS shuzhi xinhao
Platform: | Size: 328704 | Author: wzy | Hits:

[SCM] AD9956

Description: 直接频率合成器 (DDS)ad9956 单点频功能程序，用于c51单片机控制ad9956,程序为设置70M点频，用户设置不同频控码，即可设置不同频率。 -Direct frequency synthesizer (DDS) ad9956 frequency function of a single point of procedure, for the C51 single-chip control ad9956, procedures for the establishment of 70M points, frequency, user settings of different frequency control code, you can set up different frequencies.
Platform: | Size: 1024 | Author: 肖勋 | Hits:

[VHDL-FPGA-Verilog] dengjingducepin

Description: 等精度测频 FPGA程序，能实现很好的精度，最高大1HZ-FPGA, such as precision frequency measurement procedure, can achieve very good accuracy, the highest large 1Hz
Platform: | Size: 233472 | Author: 唐光敏 | Hits:

[VHDL-FPGA-Verilog] Simulate

Description: FPGA控制AD逐点采集信号，并将AD转换后的数据串行发送出去。-FPGA to control the signal sampling point by point AD, AD conversion and serial data sent.
Platform: | Size: 1024 | Author: Hongjun | Hits:

[SCM] dds

Description: 关于FPGA中DDS核参数设置的资料，英文版的XILINX资料-DDS on the FPGA in the data set of nuclear parameters, the English version of XILINX information
Platform: | Size: 1664000 | Author: 李晶 | Hits:

[VHDL-FPGA-Verilog] FPGA_Examples

Description: 《FPGA嵌入式应用系统开发典型实例》-书的光盘资料，该资料是用VHDL语言编写，作者：叶淦华-" FPGA embedded applications typical example of system development" - the book' s CD-ROM, the information is written in VHDL, the author:叶淦China
Platform: | Size: 8140800 | Author: LDP | Hits:

[VHDL-FPGA-Verilog] FPGA_SEG7_V4

Description: FPGA应用如sd卡控制，led控制，vga音频控制-Sd card FPGA applications such as control, led control, vga audio control
Platform: | Size: 93184 | Author: 钟灶生 | Hits:

[SCM] DDS

Description: 此程序使用单片机C言语编写的液晶显示及键盘输出程序，调试已通过。-Use this procedure to prepare single-chip C language of the liquid crystal display and keyboard output procedures, debugging has passed.
Platform: | Size: 1024 | Author: zhxg | Hits:

[Software Engineering] DDS-baseddesignofthesinusoidalsignalgenerator

Description: 本设计采用AT89552单片机，辅以必要的模拟电路，实现了一个基于直接数字频率合成技术(DDS)的正弦谊号发生器。设计中采用DDS芯片AD9850产生频率1KHZ~10MHZ范围内正弦波，采用功放AD811控制输出电压幅度，由单片机AT89S52控制调节步进频率1HZ。在此基础上，用模拟乘法器MC1496实现了正弦调制信号频率为1KHZ的模拟相度调制信号；用FPGA芯片产生二进制NRZ码,与AD9850结合实现相移键控PSK、幅移键控ASK、频移镇键FSK。-AT89552 the single-chip design, supplemented by the necessary analog circuits, based on the realization of a direct digital frequency synthesis (DDS) generator of sinusoidal No. Friends. The design of DDS chip AD9850 produced using 1KHZ ~ 10MHZ frequency range of sine wave, the AD811 control amplifier output voltage range of from single-chip AT89S52-conditioning step frequency control 1HZ. On this basis, the use of analog multiplier MC1496 has sinusoidal frequency modulation signal 1KHZ degree analog phase modulated signal generated by FPGA chip NRZ binary code, combined with the AD9850 to achieve phase shift keying PSK, ASK ASK, frequency Shift key town of FSK.
Platform: | Size: 208896 | Author: 何蓓 | Hits:

[VHDL-FPGA-Verilog] TUT1_BASIC1_7C5TP

Description: FPGA的89S51IP核，可以用FPGA实现51，省去了很多的麻烦-FPGA-89S51IP core
Platform: | Size: 90112 | Author: 邱柳钦 | Hits:

[VHDL-FPGA-Verilog] VHDL

Description: DDS产生正弦波（VHDL语言）用DDS产生3MHZ的正弦波,VHDL控制语言-DDS have a sine wave (VHDL language) 3MHZ generated by the DDS sine wave, VHDL control language
Platform: | Size: 1024 | Author: chenyubin | Hits:

[VHDL-FPGA-Verilog] FPGA_SOPC_starter

Description: sopc/FPGA~~！！入门~！适合初学者-sopc/FPGA ~ ~! ! Entry ~! Suitable for beginners! !
Platform: | Size: 2037760 | Author: 是得分即 | Hits:

[SCM] DDS

Description: 通过按键产生不同的波形，并能设置波形频率。-Through the keys produce different waveforms and waveform frequency settings.
Platform: | Size: 21504 | Author: 启岩 | Hits:

[VHDL-FPGA-Verilog] 67506256DDS

Description: 基于FPGA 的直接数字频率合成信号发生器(DDS)设计-FPGA-based direct digital synthesizer signal generator (DDS) design. Pdf
Platform: | Size: 2220032 | Author: 123 | Hits:

[Other] EP1C3_12_10_PHAS

Description: 基于FPGA的移相式DDS正弦信号发生器的VHDL源代码，压缩包里是在Quartus里做的工程，FPGA用的是Cyclone1C3系列-FPGA-based phase-shifting of the DDS signal generator sine VHDL source code, compressed in the bag is done in Quartus Engineering, FPGA is used Cyclone1C3 Series
Platform: | Size: 49152 | Author: deadtomb | Hits:

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[Other] fpga

[Other] DDS

[VHDL-FPGA-Verilog] AM

[VHDL-FPGA-Verilog] FPGA_signal_general

[VHDL-FPGA-Verilog] key_matrix44

[VHDL-FPGA-Verilog] ddszh

[SCM] AD9956

[VHDL-FPGA-Verilog] dengjingducepin

[VHDL-FPGA-Verilog] Simulate

[SCM] dds

[VHDL-FPGA-Verilog] FPGA_Examples

[VHDL-FPGA-Verilog] FPGA_SEG7_V4

[SCM] DDS

[Software Engineering] DDS-baseddesignofthesinusoidalsignalgenerator

[VHDL-FPGA-Verilog] TUT1_BASIC1_7C5TP

[VHDL-FPGA-Verilog] VHDL

[VHDL-FPGA-Verilog] FPGA_SOPC_starter

[SCM] DDS

[VHDL-FPGA-Verilog] 67506256DDS

[Other] EP1C3_12_10_PHAS

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